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lt3844 1 3844fb typical application features applications description high voltage, current mode switching regulator controller with programmable operating frequency n industrial power distribution n 12v and 42v automotive and heavy equipment n high voltage single board systems n distributed power systems n avionics n telecom power high voltage step-down regulator 48v to 12v, 50w ef? ciency and power loss vs load current n high voltage operation: up to 60v n output voltages up to 36v (step down) n programmable constant frequency: 100khz to 500khz n synchronizable up to 600khz n burst mode ? operation: 120a supply current n 10a shutdown supply current n 1.3% reference accuracy n drives n-channel mosfet n programmable soft-start n programmable undervoltage lockout n internal high voltage regulator for gate drive n thermal shutdown n current limit unaffected by duty cycle n 16-pin thermally enhanced tssop package the lt ? 3844 is a dc/dc controller used for medium power, low part count, high ef? ciency supplies. it offers a wide 4v to 60v input range (7.5v minimum start-up voltage) and can implement step-down, step-up, inverting and sepic topologies. the lt3844 includes burst mode operation, which reduces quiescent current below 120a and maintains high ef? - ciency at light loads. an internal high voltage bias regulator allows for simple biasing. additional features include current mode control for fast line and load transient response; programmable ? xed operating frequency that can be synchronized to an ex- ternal clock for noise sensitive applications; a gate driver capable of driving large n-channel mosfets; a precision undervoltage lockout function; 10a shutdown current; short-circuit protection and a programmable soft-start function. the lt3844 is available in a 16-lead thermally enhanced tssop package. l , lt, ltc and ltm are registered trademarks of linear technology corporation. burst mode is a registered trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5731694, 6498466, 6611131 v in shdn c ss burst_en v fb v c sync f set boost tg sw v cc pgnd sense + sense C sgnd lt3844 3844 ta01 r7 49.9k v out 12v 50w 68f 680p 22f 120pf 68f 10k 10 1000pf 0.22f 10h 33f 0.015 14.7k 130k 82.5k 1m 1f pds5100h si7850dp v in 36v to 60v load current (a) 76 82 80 78 90 88 86 84 0 3 2 1 7 6 5 4 3844 ta01b efficiency (%) power loss (w) 0.1 10 1 loss efficiency v in = 48v
lt3844 2 3844fb pin configuration absolute maximum ratings (note 1) fe package 16-lead plastic tssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 v in shdn c ss burst_en v fb v c sync f set boost tg sw v cc pgnd sense + sense C sgnd 17 t jmax = 125c, ja = 40c/w, jc = 10c/w exposed pad (pin 17) is sgnd, must be soldered to pcb order information lead free finish tape and reel part marking package description temperature range lt3844efe#pbf lt3844efe#trpbf 3844efe 16-lead plastic tssop C40c to 125c lt3844ife#pbf lt3844ife#trpbf 3844ife 16-lead plastic tssop C40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ input supply voltage (v in ) ......................... 65v to C0.3v boosted supply voltage (boost) .............. 80v to C0.3v switch voltage (sw) (note 8) ....................... 65v to C1v differential boost voltage boost to sw ........................................ 24v to C0.3v bias supply voltage (v cc ) .......................... 24v to C0.3v sense + and sense C voltages ................... 40v to C0.3v differential sense voltage sense + to sense C ..................................... 1v to C1v burst_en voltage .................................... 24v to C0.3v sync, v c , v fb , c ss and shdn voltages ...... 5v to C0.3v shdn pin currents ..................................................1ma operating junction temperature range (note 2) lt3844e (note 3) ............................... C40c to 125c lt3844i .............................................. C40c to 125c storage temperature .............................. C65c to 150c lead temperature (soldering, 10 sec) .................. 300c electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 20v, v cc = boost = burst_en = 10v, shdn = 2v, r set = 49.9k, sense C = sense + = 10v, sgnd = pgnd = sw = sync = 0v, unless otherwise noted. parameter conditions min typ max units v in operating voltage range (note 4) v in minimum start voltage v in uvlo threshold (falling) v in uvlo threshold hysteresis l l l 4 3.6 3.8 670 60 7.5 4 v v v mv v in supply current v in burst mode current v in shutdown current v cc > 9v v burst_en = 0v, v fb = 1.35v v shdn = 0v 20 20 10 15 a a a boost operating voltage range boost operating voltage range (note 5) boost uvlo threshold (rising) boost uvlo threshold hysteresis v boost C v sw v boost C v sw v boost C v sw l l 5 400 75 20 v v v mv boost supply current (note 6) boost burst mode current boost shutdown current v burst_en = 0v v shdn = 0v 1.4 0.1 0.1 ma a a
lt3844 3 3844fb electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 20v, v cc = boost = burst_en = 10v, shdn = 2v, r set = 49.9k, sense C = sense + = 10v, sgnd = pgnd = sw = sync = 0v, unless otherwise noted. parameter conditions min typ max units v cc operating voltage range (note 5) v cc output voltage v cc uvlo threshold (rising) v cc uvlo threshold hysteresis over full line and load range l l 8 6.25 500 20 8.3 v v v mv v cc supply current (note 6) v cc burst mode current v cc shutdown current v cc current limit v burst_en = 0v v shdn = 0v l l C40 1.7 95 20 C120 2.1 ma a a ma error amp reference voltage measured at v fb pin l 1.224 1.215 1.231 1.238 1.245 v v v fb pin input current v fb = 1.231v 25 na shdn enable threshold (rising) shdn threshold hysteresis l 1.3 1.35 120 1.4 v mv sense pins common mode range current limit sense voltage v sense + C v sense C l l 0 90 100 36 115 v mv input current (i sense + + i sense C ) v sense(cm) = 0v v sense(cm) = 2v v sense(cm) > 4v 350 C25 C170 a a a operating frequency l 290 270 300 310 330 khz khz minimum programmable frequency maximum programmable frequency l l 500 100 khz khz external sync frequency range l 100 600 khz sync input resistance 40 k sync voltage threshold l 1.4 2 v soft-start capacitor control current 2 a error amp transconductance l 270 340 410 s error amp dc voltage gain 62 db error amp sink/source current 30 a tg drive on voltage (note 7) tg drive off voltage c load = 2200pf c load = 2200pf 9.8 0.1 v v tg drive rise/fall time 10% to 90% or 90% to 10%, c load = 2200pf 40 ns minimum tg off time l 350 500 ns minimum tg on time l 250 350 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3844 includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. note 3: the lt3844e is guaranteed to meet performance speci? cations from 0c to 125c junction temperature. speci? cations over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3844i is guaranteed over the full C40c to 125c operating junction temperature range. note 4 : v in voltages below the start-up threshold (7.5v) are only supported when the v cc is externally driven above 6.5v. note 5: operating range is dictated by mosfet absolute maximum vgs. note 6: supply current speci? cation does not include switch drive currents. actual supply currents will be higher. note 7: dc measurement of gate drive output on voltage is typically 8.6v. internal dynamic bootstrap operation yields typical gate on voltages of 9.8v during standard switching operation. standard operation gate on voltage is not tested but guaranteed by design. note 8: the C1v absolute maximum on the sw pin is a transient condition. it is guaranteed by design and not subject to test.
lt3844 4 3844fb 3844 g01 shutdown threshold, rising (v) 1.38 1.37 1.36 1.35 1.34 1.33 1.32 temperature (c) C50 25 75 3844 g02 C25 0 50 100 125 temperature (c) C50 shutdown threshold, falling (v) 1.26 1.25 1.24 1.23 1.22 1.21 1.20 25 75 C25 0 50 100 125 3844 g05 v in (v) v cc (v) 9 8 7 6 5 4 3 4 6 8 9 57 10 11 12 3844 g07 temperature (c) C50 25 75 C25 0 50 100 125 3844 g08 v cc uvlo threshold, rising (v) 6.5 6.4 6.3 6.2 6.1 6.0 temperature (c) C50 error amp transconductance (s) 350 345 340 335 330 325 320 25 75 3844 g09 C25 0 50 100 125 i cc = 20ma t a = 25c temperature (c) C50 25 75 C25 0 50 100 125 3844 g03 8.2 8.1 8.0 7.9 7.8 7.7 7.6 7.5 v cc (v) i cc = 20ma C50 C25 100 0 50 125 25 75 temperature (c) 200 175 150 125 100 75 50 3844 g06 i cc current limit (ma) i cc(load) (ma) 0 v cc (v) 40 3844 g04 10 20 30 8.05 8.00 7.95 7.90 7.85 51525 35 t a = 25c v cc (v) 0 i cc (ma) 15 20 25 16 10 5 0 246 810 12 14 18 20 t a = 25c typical performance characteristics shutdown threshold (rising) vs temperature v cc vs temperature v cc vs i cc(load) v cc vs v in i cc current limit vs temperature v cc uvlo threshold (rising) vs temperature i cc vs v cc ( shdn = 0v) error amp transconductance vs temperature shutdown threshold (falling) vs temperature
lt3844 5 3844fb v sense (cm) (v) 0 i (sense + + sense C ) (a) 400 300 200 100 0 C100 C200 0.5 1.0 1.5 2.0 3844 g10 2.5 4.5 3.5 5.0 4.0 3.0 temperature (c) C50 25 75 3844 g12 C25 0 50 100 125 temperature (c) C50 25 75 C25 0 50 100 125 temperature (c) C50 25 75 C25 0 50 100 125 1.234 1.233 1.232 1.231 1.230 1.229 1.228 1.227 error amp reference (v) 3844 g14 3844 g15 4.54 4.52 4.50 4.48 4.46 4.44 4.42 4.40 v in uvlo threshold, rising (v) v in uvlo threshold, falling (v) 3.86 3.84 3.82 3.80 3.78 3.76 t a = 25c temperature (c) C50 current sense threshold (mv) 102 104 106 25 75 3844 g16 100 98 C25 0 50 100 125 96 94 temperature (c) C50 290 operating frequency (khz) 292 296 298 300 50 308 3844 g17 294 0 C25 75 100 25 125 302 304 306 typical performance characteristics i (sense + + sense C ) vs v sense(cm) operating frequency vs temperature error amp reference vs temperature maximum current sense threshold vs temperature v in uvlo threshold (rising) vs temperature v in uvlo threshold (falling) vs temperature pin functions v in (pin 1): the v in pin is the main supply pin and should be decoupled to sgnd with a low esr capacitor located close to the pin. shdn (pin 2): the shdn pin has a precision ic enable threshold of 1.35v (rising) with 120mv of hysteresis. it is used to implement an undervoltage lockout (uvlo) circuit. see applications information section for implementing a uvlo function. when the shdn pin is pulled below a transistor v be (0.7v), a low current shutdown mode is entered, all internal circuitry is disabled and the v in supply current is reduced to approximately 9a. typical pin input bias current is <10a and the pin is internally clamped to 6v. c ss (pin 3): the soft-start pin is used to program the supply soft-start function. use the following formula to calculate c ss for a given output voltage slew rate: c ss = 2a(t ss /1.231v) the pin should be left unconnected when not using the soft-start function.
lt3844 6 3844fb pin functions burst_en (pin 4): the burst_en pin is used to enable or disable burst mode operation. connect the burst_en pin to ground to enable the burst mode function. connect the pin to v fb or v cc to disable the burst mode function. v fb (pin 5): the output voltage feedback pin, v fb , is externally connected to the supply output voltage via a resistive divider. the v fb pin is internally connected to the inverting input of the error ampli? er. in regulation, v fb is 1.231v. v c (pin 6): the v c pin is the output of the error ampli? er whose voltage corresponds to the maximum (peak) switch current per oscillator cycle. the error ampli? er is typically con? gured as an integrator circuit by connecting an rc network from the v c pin to sgnd. this circuit creates the dominant pole for the converter regulation control loop. speci? c integrator characteristics can be con? gured to optimize transient response. when burst mode operation is enabled (see pin 4 description), an internal low imped- ance clamp on the v c pin is set at 100mv below the burst threshold, which limits the negative excursion of the pin voltage. therefore, this pin cannot be pulled low with a low impedance source. if the v c pin must be externally manipulated, do so through a 1k series resistance. sync (pin 7): the sync pin provides an external clock input for synchronization of the internal oscillator. r set is set such that the internal oscillator frequency is 10% to 25% below the external clock frequency. if unused the sync pin is connected to sgnd. for more information see oscillator sync in the applications information section of this data sheet. f set (pin 8): the f set pin programs the oscillator frequency with an external resistor, r set . the resistor is required even when supplying external sync clock signal. see the applications information section for resistor value selec- tion details. sgnd (pin 9, 17): the sgnd pin is the low noise ground reference. it should be connected to the Cv out side of the output capacitors. careful layout of the pcb is necessary to keep high currents away from this sgnd connection. see the applications information section for helpful hints on pcb layout of grounds. sense C (pin 10): the sense C pin is the negative input for the current sense ampli? er and is connected to the v out side of the sense resistor for step-down applications. the sensed inductor current limit is set to 100mv across the sense inputs. sense + (pin 11): the sense + pin is the positive input for the current sense ampli? er and is connected to the induc- tor side of the sense resistor for step-down applications. the sensed inductor current limit is set to 100mv across the sense inputs. pgnd (pin 12): the pgnd pin is the high current ground reference for internal low side switch and the v cc regulator circuit. connect the pin directly to the negative terminal of the v cc decoupling capacitor. see the applications informa- tion section for helpful hints on pcb layout of grounds. v cc (pin 13): the v cc pin is the internal bias supply decoupling node. use a low esr 1f or greater ceramic capacitor to decouple this node to pgnd. most internal ic functions are powered from this bias supply. an external diode connected from v cc to the boost pin charges the bootstrapped capacitor during the off-time of the main power switch. back driving the v cc pin from an external dc voltage source, such as the v out output of the regula- tor supply, increases overall ef? ciency and reduces power dissipation in the ic. in shutdown mode this pin sinks 20a until the pin voltage is discharged to 0v. sw (pin 14): in step-down applications the sw pin is connected to the cathode of an external clamping schottky diode, the drain of the power mosfet and the inductor. the sw node voltage swing is from v in during the on- time of the power mosfet, to a schottky voltage drop below ground during the off-time of the power mosfet. in start-up and in operating modes where there is insuf- ? cient inductor current to freewheel the schottky diode, an internal switch is turned on to pull the sw pin to ground so that the boost pin capacitor can be charged. give careful consideration in choosing the schottky diode to limit the negative voltage swing on the sw pin. tg (pin 15): the tg pin is the bootstrapped gate drive for the top n-channel mosfet. since very fast high currents are driven from this pin, connect it to the gate of the power mosfet with a short and wide, typically 0.02" width, pcb trace to minimize inductance.
lt3844 7 3844fb functional diagram pin functions boost (pin 16): the boost pin is the supply for the bootstrapped gate drive and is externally connected to a low esr ceramic boost capacitor referenced to sw pin. the recommended value of the boost capacitor, c boost , is 50 times greater than the total input capacitance of the topside mosfet. in most applications 0.1f is adequate. the maximum voltage that this pin sees is v in + v cc , ground referred. exposed pad (pin 17): sgnd. the exposed leadframe is internally connected to the sgnd pin. solder the exposed pad to the pcb ground for electrical contact and optimal thermal performance. C + C + C + C + v in uvlo (<4v) bst uvlo 8v regulator feedback reference C + C + 1.231v 3.8v regulator internal supply rail 1 9 6 v in v cc uvlo (<6v) shdn drive control nol switch logic drive control burst_en v c c ss sense C v fb 0.5v 2a 50a burst mode operation r s q oscillator slope comp generator boost tg sw v cc pgnd sync f set r set sense + sgnd boosted switch driver current sense comparator 12 7 8 13 14 10 11 5 3 100mv 4 2 16 15 v ref + 200mv soft-start burst disable driver fault condition: v in uvlo v cc uvlo v shdn uvlo c ss clamped to v fb + v be v ref ~1v C + g m error amp C + m1 d2 d3 d1 l1 (optional) r sense 3844 fd c c2 c c1 r1 ra rb v in c in r2 c boost v out c out c vcc r c
lt3844 8 3844fb operation (refer to functional diagram) the lt3844 is a pwm controller with a constant frequency, current mode control architecture. it is designed for low to medium power, switching regulator applications. its high operating voltage capability allows it to step up or down input voltages up to 60v without the need for a transformer. the lt3844 is used in nonsynchronous applications, meaning that a freewheeling recti? er diode (d1 of function diagram) is used instead of a bottom side mosfet. for circuit operation, please refer to the functional diagram of the ic and typical application on the front page of the data sheet. the lt3800 is a similar part that uses synchronous recti? cation, replacing the diode with a mosfet in a step-down application. main control loop during normal operation, the external n-channel mosfet switch is turned on at the beginning of each cycle. the switch stays on until the current in the inductor exceeds a current threshold set by the dc control voltage, v c , which is the output of the voltage control loop. the voltage control loop monitors the output voltage, via the v fb pin voltage, and compares it to an internal 1.231v reference. it increases the current threshold when the v fb voltage is below the reference voltage and decreases the current threshold when the v fb voltage is above the reference voltage. for instance, when an increase in the load current occurs, the output voltage drops causing the v fb voltage to drop relative to the 1.231v reference. the voltage control loop senses the drop and increases the current threshold. the peak inductor current is increased until the average inductor current equals the new load current and the output voltage returns to regulation. current limit/short-circuit the inductor current is measured with a series sense resistor (see the typical application on the front page). when the voltage across the sense resistor reaches the maximum current sense threshold, typically 100mv, the tg mosfet driver is disabled for the remainder of that cycle. if the maximum current sense threshold is still ex- ceeded at the beginning of the next cycle, the entire cycle is skipped. cycle skipping keeps the inductor currents to a reasonable value during a short-circuit, particularly when v in is high. setting the sense resistor value is discussed in the application information section. v cc /boosted supply an internal v cc regulator provides v in derived gate-drive power for start-up under all operating conditions with mosfet gate charge loads up to 90nc. the regulator can operate continuously in applications with v in voltages up to 60v, provided the power dissipation of the regulator does not exceed 250mw. the power dissipation is calculated as follows: p d(reg) = (v in C 8v) ? f sw ? q g where q g is the mosfet gate charge. in applications where these conditions are exceeded, v cc must be derived from an external source after start-up. maximum continuous regulator power dissipation may be exceeded for short duration v in transients. for higher converter ef? ciency and less power dissipa- tion in the ic, v cc can also be supplied from an external supply such as the converter output. when an external supply back drives the internal v cc regulator through an external diode and the v cc voltage is pulled to a diode above its regulation voltage, the internal regulator is dis- abled and goes into a low current mode. v cc is the bias supply for most of the internal ic functions and is also used to charge the bootstrapped capacitor (c boost ) via an external diode. the external mosfet switch is biased from the bootstrapped capacitor. while the external mosfet switch is off, an internal bjt switch, whose collector is connected to the sw pin and emitter is connected to the pgnd pin, is turned on to pull the sw node to pgnd and recharge the bootstrap capacitor. the switch stays on until either the start of the next cycle or until the bootstrapped capacitor is fully charged. mosfet driver the lt3844 contains a high speed boosted driver to turn on and off an external n-channel mosfet switch. the mosfet driver derives its power from the boost capaci- tor which is referenced to the sw pin and the source of the mosfet. the driver provides a large pulse of current to turn on the mosfet fast to minimize transition times. multiple mosfets can be paralleled for higher current operation.
lt3844 9 3844fb operation (refer to functional diagram) to eliminate the possibility of shoot through between the mosfet and the internal sw pull-down switch, an adap- tive nonoverlap circuit ensures that the internal pull-down switch does not turn on until the gate of the mosfet is below its turn on threshold. low current operation (burst mode operation) to increase low current load ef? ciency, the lt3844 is capable of operating in linear technologys proprietary burst mode operation where the external mosfet operates intermittently based on load current demand. the burst mode function is disabled by connecting the burst_en pin to v cc or v fb and enabled by connecting the pin to sgnd. when the required switch current, sensed via the v c pin voltage, is below 15% of maximum, burst mode operation is employed and that level of sense current is latched onto the ic control path. if the output load requires less than this latched current level, the converter will overdrive the output slightly during each switch cycle. this overdrive condition is sensed internally and forces the voltage on the v c pin to continue to drop. when the voltage on v c drops 150mv below the 15% load level, switching is disabled, and the lt3844 shuts down most of its internal circuitry, reducing total quiescent current to 120a. when the converter output begins to fall, the v c pin voltage begins to climb. when the voltage on the v c pin climbs back to the 15% load level, the ic returns to normal operation and switching resumes. an internal clamp on the v c pin is set at 100mv below the output disable threshold, which limits the negative excursion of the pin voltage, minimizing the converter output ripple during burst mode operation. during burst mode operation, the v in pin current is 20a and the v cc current is reduced to 100a. if no external drive is provided for v cc , all v cc bias currents originate from the v in pin, giving a total v in current of 120a. burst current can be reduced further when v cc is driven using an output derived source, as the v cc component of v in current is then reduced by the converter duty cycle ratio. start-up the following section describes the start-up of the supply and operation down to 4v once the step-down supply is up and running. for the protection of the lt3844 and the switching supply, there are internal undervoltage lockout (uvlo) circuits with hysteresis on v in , v cc and v boost , as shown in the electrical characteristics table. start-up and continuous operation require that all three of these undervoltage lockout conditions be satis? ed because the tg mosfet driver is disabled during any uvlo fault con- dition. in start-up, for most applications, v cc is powered from v in through the high voltage linear regulator of the lt3844. this requires v in to be high enough to drive the v cc voltage above its undervoltage lockout threshold. v cc , in turn, has to be high enough to charge the boost capacitor through an external diode so that the boost voltage is above its undervoltage lockout threshold. there is an npn switch that pulls the sw node to ground each cycle during the tg power mosfet off-time, ensuring the boost capacitor is kept fully charged. once the supply is up and running, the output voltage of the supply can backdrive v cc through an external diode. internal circuitry disables the high voltage regulator to conserve v in supply current. output voltages that are too low or too high to backdrive v cc require additional circuitry such as a voltage doubler or linear regulator. once v cc is backdriven from a supply other than v in , v in can be reduced to 4v with normal operation maintained. soft-start the soft-start function controls the slew rate of the power supply output voltage during start-up. a controlled output voltage ramp minimizes output voltage overshoot, reduces inrush current from the v in supply, and facilitates supply sequencing. a capacitor, c ss , connected from the c ss pin to sgnd, programs the slew rate. the capacitor is charged from an internal 2a current source producing a ramped voltage. the capacitor voltage overrides the internal refer- ence to the error ampli? er. if the v fb pin voltage exceeds
lt3844 10 3844fb operation (refer to functional diagram) the c ss pin voltage then the current threshold set by the dc control voltage, v c , is decreased and the inductor cur- rent is lowered. this in turn decreases the output voltage slew rate allowing the c ss pin voltage ramp to catch up to the v fb pin voltage. an internal 100mv offset is added to the v fb pin voltage relative to the to c ss pin voltage so that at start-up the soft-start circuit will discharge the v c pin voltage below the dc control voltage equivalent to zero inductor current. this will reduce the input supply inrush current. the soft-start circuit is disabled once the c ss pin voltage has been charged to 200mv above the internal reference of 1.231v. during a v in uvlo, v cc uvlo or shdn uvlo event, the c ss pin voltage is discharged with a 50a current source. in normal operation the c ss pin voltage is clamped to a diode above the v fb pin voltage. therefore, the value of the c ss capacitor is relevant in how long of a fault event will retrigger a soft-start. in other words, if any of the above uvlo conditions occur, the c ss pin voltage will be discharged with a 50a current source. there is a diode worth of voltage headroom to ride through the fault before the c ss pin voltage enters its active region and the soft- start function is enabled. also, since the c ss pin voltage is clamped to a diode above the v fb pin voltage, during a short circuit the c ss pin volt- age is pulled low because the v fb pin voltage is low. once the short has been removed the v fb pin voltage starts to recover. the soft-start circuit takes control of the output voltage slew rate once the v fb pin voltage has exceeded the slowly ramping c ss pin voltage, reducing the output voltage overshoot during a short-circuit recovery. slope/antislope compensation the ic incorporates slope compensation to eliminate potential subharmonic oscillations in the current control loop. the ics slope compensation circuit imposes an arti? cial ramp on the sensed current to increase the rising slope as duty cycle increases. typically, this additional ramp affects the sensed current value, thereby reducing the achievable current limit value by the same amount as the added ramp represents. as such, the current limit is typically reduced as the duty cycle increases. the lt3844, however, contains antislope com- pensation circuitry to eliminate the current limit reduction associated with slope compensation. as the slope compen- sation ramp is added to the sensed current, a similar ramp is added to the current limit threshold. the end result is that the current limit is not compromised so the lt3844 can provide full power regardless of required duty cycle. shutdown the lt3844 includes a shutdown mode where all the internal ic functions are disabled and the v in current is reduced to less than 10a. the shutdown pin can be used for undervoltage lockout with hysteresis, micropower shut- down or as a general purpose on/off control of the converter output. the shutdown function has two thresholds. the ? rst threshold, a precision 1.23v threshold with 120mv of hysteresis, disables the converter from switching. the second threshold, approximately a 0.7v referenced to sgnd, completely disables all internal circuitry and reduces the v in current to less than 10a. see the application information section for more information. applications information the basic lt3844 step-down (buck) application, shown in the typical application on the front page, converts a larger positive input voltage to a lower positive or negative output voltage. this application information section assists selection of external components for the requirements of the power supply. r sense selection the current sense resistor, rs ense , monitors the inductor current of the supply (see typical application on front page). its value is chosen based on the maximum required output load current. the lt3844 current sense ampli? er has a maximum voltage threshold of, typically, 100mv.
lt3844 11 3844fb applications information therefore, the peak inductor current is 100mv/r sense . the maximum output load current, i out(max) , is the peak inductor current minus half the peak-to-peak ripple cur- rent, i l . allowing adequate margin for ripple current and exter- nal component tolerances, r sense can be calculated as follows: r mv i sense out max = 70 () typical values for r sense are in the range of 0.005 to 0.05. operating frequency the choice of operating frequency and inductor value is a trade off between ef? ciency and component size. low frequency operation improves ef? ciency by reducing mosfet switching losses and gate charge losses. however, lower frequency operation requires more inductance for a given amount of ripple current, resulting in a larger induc- tor size and higher cost. if the ripple current is allowed to increase, larger output capacitors may be required to maintain the same output ripple. for converters with high step-down v in -to-v out ratios, another consideration is the minimum on-time of the lt3844 (see the minimum on-time considerations section). a ? nal consideration for operating frequency is that in noise-sensitive com- munications systems, it is often desirable to keep the switching noise out of a sensitive frequency band. the lt3844 uses a constant frequency architecture that can be programmed over a 100khz to 500khz range with a single resistor from the f set pin to ground, as shown in figure 1. the nominal voltage on the f set pin is 1v and the current that ? ows from this pin is used to charge an internal oscillator capacitor. the value of r set for a given operating frequency can be chosen from figure 4 or from the following equation: rk f set sw () .? ? (C . ) = 84 10 4131 table 1 lists typical resistor values for common operating frequencies: table 1. recommended 1% standard values r set f sw 191k 100khz 118k 150khz 80.6k 200khz 63.4k 250khz 49.9k 300khz 40.2k 350khz 33.2k 400khz 27.4k 450khz 23.2k 500khz step-down converter: inductor selection the critical parameters for selection of an inductor are minimum inductance value, volt-second product, satura- tion current and/or rms current. for a given i, the minimum inductance value is calculated as follows: lv vv fv i out in max out sw in max l ? C ?? () () f sw is the switch frequency. frequency (khz) 0 20 r set (k) 40 80 100 120 400 200 3844 g19 60 200 100 500 300 600 140 160 180 figure 1. timing resistor (r set ) value
lt3844 12 3844fb applications information the typical range of values for i l is (0.2 ? i out(max) ) to (0.5 ? i out(max) ), where i out(max) is the maximum load current of the supply. using i l = 0.3 ? i out(max) yields a good design compromise between inductor performance versus inductor size and cost. a value of i l = 0.3 ? i out(max) produces a 15% of i out(max) ripple current around the dc output current of the supply. lower values of i l require larger and more costly magnetics. higher values of i l will increase the peak currents, requiring more ? ltering on the input and output of the supply. if i l is too high, the slope compensation circuit is ineffective and current mode instability may occur at duty cycles greater than 50%. to satisfy slope compensation requirements the minimum inductance is calculated as follows: lv dc dc r f out max max sense sw > ? C ? ?. 21 833 some magnetics vendors specify a volt-second product in their data sheet. if they do not, consult the magnetics vendor to make sure the speci? cation is not being exceeded by your design. the volt-second product is calculated as follows: volt-second (sec) = (C)? () vvv v in max out out i n n max sw f () ? the magnetics vendors specify either the saturation cur- rent, the rms current or both. when selecting an inductor based on inductor saturation current, use the peak cur- rent through the inductor, i out(max) + i l /2. the inductor saturation current speci? cation is the current at which the inductance, measured at zero current, decreases by a speci? ed amount, typically 30%. when selecting an inductor based on rms current rating, use the average current through the inductor, i out(max) . the rms current speci? cation is the rms current at which the part has a speci? c temperature rise, typically 40c, above 25c ambient. after calculating the minimum inductance value, the volt-second product, the saturation current and the rms current for your design, select an off-the-shelf inductor. contact the application group at linear technology for further support. for more detailed information on selecting an inductor, please see the inductor selection section of linear technology application note 44. step-down converter: mosfet selection the selection criteria of the external n-channel standard level power mosfet include on resistance(r ds(on) ), re- verse transfer capacitance (c rss ), maximum drain source voltage (v dss ), total gate charge (q g ) and maximum continuous drain current. for maximum ef? ciency, minimize r ds(on) and c rss . low r ds(on) minimizes conduction losses while low c rss minimizes transition losses. the problem is that r ds(on) is inversely related to c rss . balancing the transition losses with the conduction losses is a good idea in sizing the mosfet. select the mosfet to balance the two losses. calculate the maximum conduction losses of the mosfet: pi v v r cond out max out in ds on = ? ? ? ? ? ? () () () () 2 note that r ds(on) has a large positive temperature depen- dence. the mosfet manufacturers data sheet contains a curve, r ds(on) vs temperature. calculate the maximum transition losses: p tran = (k)(v in ) 2 (i out(max) )(c rss )(f sw ) where k is a constant inversely related to the gate driver current, approximated by k = 2 for lt3844 applications. the total maximum power dissipation of the mosfet is the sum of these two loss terms: p fet(total) = p cond + p tran to achieve high supply ef? ciency, keep the p fet(total) to less than 3% of the total output power. also, complete a thermal analysis to ensure that the mosfet junction temperature is not exceeded. t j = t a + p fet(total) ? ja where ja is the package thermal resistance and t a is the ambient temperature. keep the calculated t j below the max- imum speci? ed junction temperature, typically 150c.
lt3844 13 3844fb applications information note that when v in is high and f sw is high, the transition losses may dominate. a mosfet with higher r ds(on) and lower c rss may provide higher ef? ciency. mosfets with higher voltage v dss speci? cation usually have higher r ds(on) and lower c rss . choose the mosfet v dss speci? cation to exceed the maximum voltage across the drain to the source of the mosfet, which is v in(max) plus any additional ringing on the switch node. ringing on the switch node can be greatly reduced with good pcb layout and, if necessary, an rc snubber. the internal v cc regulator is capable of sourcing up to 40ma which limits the maximum total mosfet gate charge, q g , to 40ma/f sw . the q g vs v gs speci? cation is typically provided in the mosfet data sheet. use q g at v gs of 8v. if v cc is back driven from an external supply, the mosfet drive current is not sourced from the internal regulator of the lt3844 and the q g of the mosfet is not limited by the ic. however, note that the mosfet drive current is supplied by the internal regulator when the external supply back driving v cc is not available such as during start-up or short-circuit. the manufacturers maximum continuous drain current speci? cation should exceed the peak switch current, i out(max) + i l /2. during the supply start-up, the gate drive levels are set by the v cc voltage regulator, which is approximately 8v. once the supply is up and running, the v cc can be back driven by an auxiliary supply such as v out . it is important not to exceed the manufacturers maximum v gs speci? cation. a standard level threshold mosfet typically has a v gs maximum of 20v. step-down converter: recti? er selection the recti? er diode (d1 on the functional diagram) in a buck converter generates a current path for the inductor current when the main power switch is turned off. the recti? er is selected based upon the forward voltage, re- verse voltage and maximum current. a schottky diode is recommended. its low forward voltage yields the lowest power loss and highest ef? ciency. the maximum reverse voltage that the diode will see is v in(max) . in continuous mode operation, the average diode cur- rent is calculated at maximum output load current and maximum v in : ii vv v diode avg out max in max out in max () ( ) () () = ? to improve ef? ciency and to provide adequate margin for short-circuit operation, a diode rated at 1.5 to 2 times the maximum average diode current, i diode(avg) , is recommended. step-down converter: input capacitor selection a local input bypass capacitor is required for buck convert- ers because the input current is pulsed with fast rise and fall times. the input capacitor selection criteria are based on the bulk capacitance and rms current capability. the bulk capacitance will determine the supply input ripple voltage. the rms current capability is used to keep from overheating the capacitor. the bulk capacitance is calculated based on maximum input ripple, v in : c iv vf v in bulk out max out in sw in min () () () ? ?? = v in is typically chosen at a level acceptable to the user. 100mv to 200mv is a good starting point. aluminum elec- trolytic capacitors are a good choice for high voltage, bulk capacitance due to their high capacitance per unit area. the capacitors rms current is: ii vvv v cin rms out out in out in () (C ) () = 2 if applicable, calculate it at the worst-case condition, v in = 2v out . the rms current rating of the capacitor is speci? ed by the manufacturer and should exceed the calculated i cin(rms) . due to their low esr (equivalent series resistance), ceramic capacitors are a good choice for high voltage, high rms current handling. note that the ripple current ratings from aluminum electrolytic capacitor manufacturers are based on 2000 hours of life. this makes
lt3844 14 3844fb applications information it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. the combination of aluminum electrolytic capacitors and ceramic capacitors is an economical approach to meet- ing the input capacitor requirements. the capacitor volt- age rating must be rated greater than v in(max) . multiple capacitors may also be paralleled to meet size or height requirements in the design. locate the capacitor very close to the mosfet switch and use short, wide pcb traces to minimize parasitic inductance. step-down converter: output capacitor selection the output capacitance, c out , selection is based on the designs output voltage ripple, v out and transient load requirements. v out is a function of i l and the c out esr. it is calculated by: = + ? ? ? ? ? ? viesr fc out l sw out ? (? ? ) 1 8 the maximum esr required to meet a v out design requirement can be calculated by: esr max vlf v v v out sw out out in max () ()()() ?C () = 1 ? ? ? ? ? ? ? worst-case v out occurs at highest input voltage. use paralleled multiple capacitors to meet the esr require- ments. increasing the inductance is an option to lower the esr requirements. for extremely low v out , an ad- ditional lc ? lter stage can be added to the output of the supply. application note 44 has some good tips on sizing an additional output ? lter. output voltage programming a resistive divider sets the dc output voltage according to the following formula: rr v v out 21 1 231 1 = ? ? ? ? ? ? . C the external resistor divider is connected to the output of the converter as shown in figure 2. tolerance of the feedback resistors will add additional error to the output voltage. example: v out = 12v; r1 = 10k rk v v kuse k 210 12 1 231 1 8748 866 1 =? ? ? ? ? ? ? =? . ..% the v fb pin input bias current is typically 25na, so use of extremely high value feedback resistors could cause a converter output that is slightly higher than expected. bias current error at the output can be estimated as: v out(bias) = 25na ? r2 supply uvlo and shutdown the shdn pin has a precision voltage threshold with hysteresis which can be used as an undervoltage lockout threshold (uvlo) for the power supply. undervoltage lockout keeps the lt3844 in shutdown until the supply input voltage is above a certain voltage programmed by the user. the hysteresis voltage prevents noise from falsely tripping uvlo. resistors are chosen by ? rst selecting r b . then: rr v v ab supply on = ? ? ? ? ? ? ? . C () 135 1 l1 v fb pin r2 r1 v out c out 3844 f02 shdn pin r a r b v supply 3844 f03 figure 2. output voltage feedback divider figure 3. undervoltage lockout circuit
lt3844 15 3844fb applications information v supply(on) is the input voltage at which the undervoltage lockout is disabled and the supply turns on. example: select r b = 49.9k, v supply(on) = 14.5v (based on a 15v minimum input voltage) rk v v a = ? ? ? ? ? ? 49 9 14 5 135 1 .? . . C = 486.1k (499k resistor is selected) if low supply current in standby mode is required, select a higher value of r b . the supply turn off voltage is 9% below turn on. in the example the v supply(off) would be 13.2v. if additional hysteresis is desired for the enable function, an external positive feedback resistor can be used from the lt3844 regulator output. the shutdown function can be disabled by connecting the shdn pin to the v in through a large value pull-up resistor. this pin contains a low impedance clamp at 6v, so the shdn pin will sink current from the pull-up resistor(r pu ): i shdn = vv r in pu C6 because this arrangement will clamp the shdn pin to the 6v, it will violate the 5v absolute maximum voltage rating of the pin. this is permitted, however, as long as the absolute maximum input current rating of 1ma is not exceeded. input shdn pin currents of <100a are recommended: a 1m or greater pull-up resistor is typically used for this con? guration. soft-start the desired soft-start time (t ss ) is programmed via the c ss capacitor as follows: c at v ss ss = 2 1 231 ? . the amount of time in which the power supply can withstand a v in , v cc or v shdn uvlo fault condition (t fault ) before the c ss pin voltage enters its active region is approximated by the following formula: t cv a fault ss = ?. 065 50 oscillator sync the oscillator can be synchronized to an external clock. set the r set resistor at least 10% below the desired sync frequency. it is recommended that the sync pin be driven with a square wave that has amplitude greater than 2v, pulse width greater than 1ms and rise time less than 500ns. the rising edge of the sync wave form triggers the discharge of the internal oscillator capacitor. ef? ciency considerations the ef? ciency of a switching regulator is equal to the output power divided by the input power times 100%. express percent ef? ciency as: % ef? ciency = 100% - (l1 + l2 + l3 + ...) where l1, l2, etc. are individual loss terms as a percent- age of input power. although all dissipative elements in the circuit produce losses, four main contributors usually account for most of the losses in lt3844 circuits: 1. lt3844 v in and v cc current loss 2. i 2 r conduction losses 3. mosfet transition loss 4. schottky diode conduction loss 1. the v in and v cc currents are the sum of the quiescent currents of the lt3844 and the mosfet drive currents. the quiescent currents are in the lt3844 electrical char- acteristics table. the mosfet drive current is a result of charging the gate capacitance of the power mosfet each cycle with a packet of charge, q g . q g is found in the mosfet data sheet. the average charging current is calculated as q g ? f sw . the power loss term due to these currents can be reduced by backdriving v cc with a lower voltage than v in such as v out .
lt3844 16 3844fb applications information 2. i 2 r losses are calculated from the dc resistances of the mosfet, the inductor, the sense resistor and the input and output capacitors. in continuous conduction mode the average output current ? ows through the inductor and r sense but is chopped between the mosfet and the schottky diode. the resistances of the mosfet (r ds(on) ) and the r sense multiplied by the duty cycle can be summed with the resistances of the inductor and r sense to obtain the total series resistance of the circuit. the total conduction power loss is proportional to this resistance and usually accounts for between 2% to 5% loss in ef? ciency. 3. transition losses of the mosfet can be substantial with input voltages greater than 20v. see mosfet selection section. 4. the schottky diode can be a major contributor of power loss especially at high input to output voltage ratios (low duty cycles) where the diode conducts for the majority of the switch period. lower v f reduces the losses. note that oversizing the diode does not always help because as the diode heats up the v f is reduced and the diode loss term is decreased. i 2 r losses and the schottky diode loss dominate at high load currents. other losses including c in and c out esr dissipative losses and inductor core losses generally account for less than 2% total additional loss in ef? ciency. pcb layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation. these items are illustrated graphically in the layout diagram of figure 3. 1. keep the signal and power grounds separate. the signal ground consists of the lt3844 sgnd pin, the exposed pad on the backside of the lt3844 ic and the (C) terminal of v out . the signal ground is the quiet ground and does not contain any high, fast currents. the power ground consists of the schottky diode anode, the (C) terminal of the input capacitor and the ground return of the v cc capacitor. this ground has very fast high currents and is considered the noisy ground. the two grounds are connected to each other only at the (C) terminal of v out . 2. use short wide traces in the loop formed by the mosfet, the schottky diode and the input capacitor to minimize high frequency noise and voltage stress from parasitic inductance. surface mount components are preferred. 3. connect the v fb pin directly to the feedback resistors independent of any other nodes, such as the sense C pin. connect the feedback resistors between the (+) and (C) terminals of c out . locate the feedback resistors in close proximity to the lt3844 to keep the high impedance node, v fb , as short as possible. 4. route the sense C and sense + traces together and keep as short as possible. 5. locate the v cc and boost capacitors in close proximity to the ic. these capacitors carry the mosfet drivers high peak currents. place the small-signal components away from high frequency switching nodes (boost, sw and tg). in the layout shown in figure 3, place all the small-signal components on one side of the ic and all the power components on the other. this helps to keep the signal and power grounds separate. 6. a small decoupling capacitor (100pf) is sometimes useful for ? ltering high frequency noise on the feedback and sense nodes. if used, locate as close to the ic as possible. 7. the lt3844 packaging will ef? ciently remove heat from the ic through the exposed pad on the backside of the part. the exposed pad is soldered to a copper footprint on the pcb. make this footprint as large as possible to improve the thermal resistance of the ic case to ambient air. this helps to keep the lt3844 at a lower temperature. 8. make the trace connecting the gate of mosfet m1 to the tg pin of the lt3844 short and wide.
lt3844 17 3844fb applications information 3 c boost r sense r a r c r set r2 r1 r b v in C v in + v in shdn sync f set c ss burst_en v fb v c sgnd boost tg sw v cc pgnd sense + sense C + C l1 m1 d3 3844 f04 lt3844 1 2 4 5 6 7 8 9 16 15 14 13 12 11 10 d2 d1 c vcc c in c out v out c c2 c ss c c1 17 figure 4. lt3844 layout diagram (see pcb layout checklist)
lt3844 18 3844fb applications information minimum on-time considerations (buck mode) minimum on-time, t on(min) , is the smallest amount of time that the lt3844 is capable of turning the top mosfet on and off again. it is determined by internal timing delays and the amount of gate charge required turning on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t v vf t on out in sw on min => ? () where t on(min) is typically 350ns worst case. if the duty cycle falls below what can be accommodated by the minimum on-time, the lt3844 will begin to skip cycles. the output will be regulated, but the ripple current and ripple voltage will increase. if lower frequency operation is acceptable, the on-time can be increased above t on(min) for the same step-down ratio. boost converter design the lt3844 can be used to con? gure a boost converter to step-up voltages to as high as hundreds of volts. an example of a boost converter circuit schematic is shown in the typical applications section. the following sections are a guide to designing a boost converter: the maximum duty cycle of the main switch is: dc vv v max out in min out = ? () boost converter: inductor selection the critical parameters for selection of an inductor are minimum inductance value and saturation current. the minimum inductance value is calculated as follows: l v if dc min in min lsw max = () ? ? f sw is the switch frequency. similar to the buck converter, the typical range of values for i l is (0.2 ? i l(max) ) to (0.5 ? i l(max) ), where i l(max) is the maximum average inductor current. ii v v l max out max out in min () () () ? = using i l = 0.3 ? i l(max) yields a good design compromise between inductor performance versus inductor size and cost. the inductor must not saturate at the peak operating current, i l(max) + i l /2. the inductor saturation current speci? cation is the current at which the inductance, mea- sured at zero current, decreases by a speci? ed amount, typically 30%. one drawback of boost regulators is that they cannot be current limited for output shorts because the current steer- ing diode makes a direct connection between input and output. therefore, the inductor current during an output short circuit is only limited by the available current of the input supply. after calculating the minimum inductance value and the saturation current for your design, select an off-the-shelf inductor. for more detailed information on selecting an inductor, please see the inductor selection section of linear technology application note 19. boost converter: mosfet selection the selection criteria of the external n-channel standard level power mosfet include on resistance (r ds(on) ), re- verse transfer capacitance (c rss ), maximum drain source voltage (v dss ), total gate charge (q g ) and maximum continuous drain current. for maximum ef? ciency, minimize r ds(on) and c rss . low r ds(on) minimizes conduction losses while low c rss minimizes transition losses. the problem is that r ds(on) is inversely related to c rss . balancing the tran- sition losses with the conduction losses is a good idea in sizing the mosfet. select the mosfet to balance the
lt3844 19 3844fb applications information two losses. calculate the maximum conduction losses of the mosfet: pdc i dc r cond max out max max ds on = ? ? ? ? ? ? ? () () ? 1 note that r ds(on) has large positive temperature depen- dence. the mosfet manufacturers data sheet contains a curve, r ds(on) vs temperature. calculate the maximum transition losses: p kv i c f dc tran out out max rss sw = ()( ) () ()() ? 2 1 () ( m max ) where k is a constant inversely related to the gate driver current, approximated by k = 2 for lt3844 applications. the total maximum power dissipation of the mosfet is the sum of these two loss terms: p fet(total) = p cond + p tran to achieve high supply ef? ciency, keep the p fet(total) to less than 3% of the total output power. also, complete a thermal analysis to ensure that the mosfet junction temperature is not exceeded. t j = t a + p fet(total) ? ja where ja is the package thermal resistance and t a is the ambient temperature. keep the calculated t j below the maximum speci? ed junction temperature, typically 150c. note that when v out is high (>20v), the transition losses may dominate. a mosfet with higher r ds(on) and lower c rss may provide higher ef? ciency. mosfets with higher voltage v dss speci? cation usually have higher r ds(on) and lower c rss . choose the mosfet v dss speci? cation to exceed the maximum voltage across the drain to the source of the mosfet, which is v out plus the forward voltage of the recti? er, typically less than 1v. the internal v cc regulator is capable of sourcing up to 40ma which limits the maximum total mosfet gate charge, q g , to 40ma / f sw . the q g vs v gs speci? cation is typically provided in the mosfet data sheet. use q g at v gs of 8v. if v cc is back driven from an external supply, the mosfet drive current is not sourced from the internal regulator of the lt3844 and the q g of the mosfet is not limited by the ic. however, note that the mosfet drive current is supplied by the internal regulator when the external supply back driving v cc is not available such as during start-up or short-circuit. the manufacturers maximum continuous drain current speci? cation should exceed the peak switch current which is the same as the inductor peak current, i l(max) + i l /2. during the supply start-up, the gate drive levels are set by the v cc voltage regulator, which is approximately 8v. once the supply is up and running, the v cc can be back driven by an auxiliary supply such as v out . it is important not to exceed the manufacturers maximum v gs speci? cation. a standard level threshold mosfet typically has a v gs maximum of 20v. boost converter: recti? er selection the recti? er is selected based upon the forward voltage, reverse voltage and maximum current. a schottky diode is recommended for its low forward voltage and yields the lowest power loss and highest ef? ciency. the maximum reverse voltage that the diode will see is v out . the average diode current is equal to the maximum output load current, i out(max) . a diode rated at 1.5 to 2 times the maximum average diode current is recommended. remember boost converters are not short-circuit protected. boost converter: output capacitor selection in boost mode, the output capacitor requirements are more demanding due to the fact that the current waveform is pulsed instead of continuous as in a buck converter. the choice of component(s) is driven by the acceptable ripple voltage which is affected by the esr, esl and bulk capacitance. the total output ripple voltage is: vi fc esr dc out out max sw out max =+ ? ? ? ? ? ? ? () ? 1 1 where the ? rst term is due to the bulk capacitance and the second term due to the esr.
lt3844 20 3844fb applications information the choice of output capacitor is also driven by the rms ripple current requirement. the rms ripple current is: ii vv v rms cout out max out in min in min () () () () ? = ? at lower output voltages (<30v) it may be possible to sat- isfy both the output ripple voltage and rms requirements with one or more capacitors of a single type. however, at output voltages above 30v where capacitors with both low esr and high bulk capacitance are hard to ? nd, the best approach is to use a combination of aluminum electrolytic and ceramic capacitors. the low esr ceramic capacitor will minimize the esr while the aluminum electrolytic capacitor will supply the required bulk capacitance. boost converter: input capacitor selection the input capacitor of a boost converter is less critical than the output capacitor, due to the fact that the inductor is in series with the input and the input current waveform is continuous. the input voltage source impedance de- termines the size of the input capacitor, which is typically in the range of 10f to 100f. a low esr capacitor is recommended though not as critical as with the output capacitor. the rms input capacitor ripple current for a boost converter is: i v lf dc rms cin in min sw max () () .? ? ? = 03 please note that the input capacitor can see a very high surge current when a battery is suddenly connected to the input of the converter and solid tantalum capacitors can fail catastrophically under these conditions. be sure to specify surge-tested capacitors. boost converter: r sense selection the boost application in the typical applications section has the location of the current sense resistor in series with the inductor with one side referenced to v in . this location was chosen for two reasons. firstly, the circulating current is always monitored so in the case of an output overvoltage or input overcurrent condition the main switch will skip cycles to protect the circuitry. secondly, the v in node can be considered low noise since it is heavily ? ltered and the input current is not pulsed but continuous. in the case where the input voltage exceeds the voltage limits on the lt3844 sense pins, the sense resistor can be moved to the source of the mosfet. in both cases the resistor value is the calculated using the same formula. the lt3844 current comparator has a maximum threshold of 100mv/r sense . the current comparator threshold sets the peak of the inductor current. allowing adequate margin for ripple current and external component tolerances, r sense can be calculated as follows: r mv i sense lmax = 70 () where i l(max) is the maximum average inductor current as calculated in the boost converter: inductor selection section.
lt3844 21 3844fb typical applications all ceramic capacitor application, 24v to 3.3v at 5a, f sw = 250khz v in shdn c ss burst_en v fb v c sync f set boost tg sw v cc pgnd sense + sense C sgnd lt3844 3844 ta02 r5 63.4k v out 3.3v 5a c2 680pf c3 100pf c in 22f s 3 r4 10k c1 2200pf c5 0.22f c4 2.2f l1 6.8h c out 100f s 2 r sense 0.01 r1 3.32k r2 5.62k r3 1m d1 d2 in4148 m1 v in 24v l1 = vishay, ihlp5050fd-01 m1 = vishay, si7852dp d1 = diodes inc, pds760 c out = tdk, c4532x5r0j107k c in = tdk, c4532x7r2a225k (voltage transients up to 60v) 4 1 3 2 5 6 7 8 16 15 14 13 12 11 10 9 8v to 20v to 8v, 25w sepic application v in shdn c ss burst_en v fb v c sync f set boost tg sw v cc pgnd sense + sense C sgnd lt3844 3844 ta03 r3 49.9k v out 8v 25w c2 100pf c3 680pf c in2 1f 25v c in1 22f 25v s 3 c1 3300pf c5 22mf 25v s 3 c4 1f 25v r1 10k r2 54.9k r4 1m r sense 0.01 r5 40.2k d2 r6 10 r7 10 m1 v in 12v l1 = coiltronics, versapac vp5-0083 c in , c5, c out2 = tdk, c4532x7r1e226m d2 = onsemi, mbrd660 c out = sanyo os-con, 16svp330m c in = vishay, si7852dp 56pf c out2 22f 25v c out1 330f 16v ? ? l1 l1 4 1 3 2 5 6 7 8 16 15 14 13 12 11 10 9 +
lt3844 22 3844fb typical applications two phase spread spectrum 24v input to 12v, 6a output v in shdn c ss burst_en v fb v c sync f set boost tg sw v cc pgnd sense + sense C sgnd lt3844 r5 49.9k r21 49.9k r22 10k v out 12v 6a c2 680pf c13 47pf r4 4.99k c1 2200pf c5 0.22f 16v c4 2.2f l1 15h c out 22f 25v r sense 0.02 r1 10k c in 6.8f 50v s 3 r2 87.5k r3 3m r6 270k r13 3m r16 270k d1 d1a bav70 d11a bav70 d1b bav70 m1 v in shdn c ss burst_en v fb v c sync f set boost tg sw v cc pgnd sense + sense C sgnd lt3844 3844 ta04 r15 49.9k c11 2200pf c15 0.22f 16v c14 2.2f l1 15h r sense 0.02 r11 10k r12 87.5k d11 m11 l1, l11 = vishay, ihlp5050fd-01 m1, m11 = vishay, si7850dp d1, d11 = diodes inc, pds760 c out = tdk, c4532x7r1e226k c in = tdk, c4532x7r1h685k v+ div ph out1 set mod gnd out2 out v in gnd ltc6902 lt1121-5 v in 18v to 36v d11b bav70 4 1 3 2 5 6 7 8 16 15 14 13 12 11 10 9 4 1 1 3 3 2 2 5 6 7 8 16 15 14 13 12 11 10 9 10 9 8 5 1 2 3 4 sync1 sync2 sync1 sync2
lt3844 23 3844fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. fe16 (bc) tssop 0204 0.09 C 0.20 (.0035 C .0079) 0 C 8 0.25 ref 0.50 C 0.75 (.020 C .030) 4.30 C 4.50* (.169 C .177) 134 5 6 7 8 10 9 4.90 C 5.10* (.193 C .201) 16 1514 13 12 11 1.10 (.0433) max 0.05 C 0.15 (.002 C .006) 0.65 (.0256) bsc 2.94 (.116) 0.195 C 0.30 (.0077 C .0118) typ 2 recommended solder pad layout 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 2.94 (.116) 3.58 (.141) 3.58 (.141) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc package description fe package 16-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation bc
lt3844 24 3844fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt 0309 rev b ? printed in usa related parts typical application 12v to 48v 50w step-up converter with 400khz switching frequency 4 r6 40k r2 383k r1 10k v in c ss burst_en v fb v c sync f set boost tg sw v cc pgnd sense + sense C sgnd m1 d2 3844 ta05 lt3844 shdn 1 3 2 5 6 7 8 16 15 14 13 12 11 10 9 c3 4700pf c2 120pf c5 2.2f 25v c4 4700pf c1 0.1f 25v c out1 330f c out2 220f m1 = vishay, si7370dp l1 = vishay, ihlp5050fd-01 d2 = diodes inc., pds560 c in = sanyo, 25svp33m c out1 = sanyo, 63ce220fst c out2 = tdk, c4532x7r2a225k r sense = irc, lrf2512-01-r010-f c in 33f 25v s 2 v in 12v r sense 0.01 l1 6.8h v out 48v 50w d1 bav99 r4 4.7m r5 33.2k + + part number description comments lt1339 high power synchronous dc/dc controller v in up to 60v, drivers 10000pf gate capacitance, i out < 20a ltc1624 switching controller buck, boost, sepic, 3.5v v in 36v; 8-lead so package ltc1702a dual 2-phase synchronous dc/dc controller 550khz operation, no r sense , 3v < v in < 7v, i out < 20a ltc1735 synchronous step-down dc/dc controller 3.5v < v in < 36v, 0.8v < v out < 6v, current mode, i out < 20a ltc1778 no r sense synchronous dc/dc controller 4v < v in < 36v, fast transient response, current mode, i out < 20a lt3010 50ma, 3v to 80v linear regulator 1.275v < v out < 60v, no protection diode required, 8-lead msop package lt3430/lt3431 monolithic 3a, 200khz/500khz step-down regulator 5.5v < v in < 60v, 0.1 saturation switch, 16-lead ssop package lt c ? 3703/ltc3703-5 100v synchronous switching regulator controllers no r sense , voltage mode control, gn16 package lt3724 high voltage current mode switching regulator controllers v in up to 60v, i out 5a, 16-lead tssop fe package, onboard bias regulator, burst mode operation, 200khz operation lt3800 high voltage synchronous regulator controller v in up to 60v, i out 20a, current mode, onboard bias regulator, burst mode operation, 16-lead tssop fe package

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